Serializer/Deserializers (Ser/Des) are devices that can take wide bit-width, single-ended signal buses and compress them to a few, and often times one, differential signal that switches at a much higher frequency rate than the wide single-ended data bus. A SerDes is often used in high-speed communication networks and is typically an Integrated Circuit (IC) transceiver. In other words, the SerDes provides the interface between a core of an IC or similar processor core and the communication channel used to carry information to/from the core of the IC or processor.
Thirty years ago, the operational speed of the IC or processor core usually exceeded the speed with which information could be carried to/from the IC or processor core. However, advances in high-speed communication network technologies have caused the communication channel to operate at much higher speeds (e.g., gigabit or multi-gigabit speeds) than the IC or processor core. Accordingly, the SerDes is needed to parallelize and slow down the data received on the communication channel before it can be fed to the IC or processor core.
Problematically, most SerDes consume a significant amount of power, even though they represent a small portion of the overall IC or processor. Additionally, most SerDes are specifically designed to output data at a single bus width. It would be advantageous to provide a SerDes solution that consumes less power and is capable of outputting multiple output bus widths.